This invention relates generally to semiconductor memory arrays, and more particularly the invention relates to a flash EPROM cell and array.
The EPROM cell is an electrically programmable device in which charge is selectively captured on a floating gate positioned between the control gate and the channel region of a field-effect transistor. In programming the floating gate, hot electron channel current injection results from applying a high voltage on the control gate and the drain. Electrons from the channel current are injected to the floating gate and cause V.sub.t of the transistor to increase. A programmed EPROM is erased by applying ultraviolet light to the device. Therefore, packaged EPROM devices require a window in the package for illuminating the semiconductor device with ultraviolet light.
The EEPROM memory cell is electrically programmable and electrically erasable A thin oxide is provided between a floating gate and either the source or drain electrode to permit the tunneling of electrons through the oxide for programming and erasing the cell. However, while the EEPROM obviates the need for ultraviolet light radiation in erasing a cell, the cell structure is larger due to the need for a select transistor cascoded to the memory transistor for proper bit erasure.
Flash EEPROM structures are known in which an entire memory array can be erased at the same time during an erase operation. Electron tunneling is employed in the erasing of the cells. The need for a thin tunneling oxide as well as the use of split gate structures in which the control gate overlaps the floating gate leads to production yield problems a well as increased cell size.